By Jeffrey Liker, David Meier
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Extra resources for The Test access port and boundary-scan architecture
13] R. Keeler, "Chip-on-Board Alters the Landscape of a PC Board," Electronic Packaging and Production, Vol. 25, July 7th 1985, pp. 62-67. L. Ginsberg, "Chip and Wire Technology: The Ultimate in Surface Mounting," Electronic Packaging and Production, Vol. 25, August 8th 1985, pp. 78-83.  K. Gilleo, "Direct Chip Interconnect Using Polymer Bonding," Electronic Components Conference Proceedings, IEEE, New York, 1989, pp. 37-44. J. M. A. Teneketges, "Multichip Packaging Design for VLSI Based Systems," Electronics Components Conference Proceedings, IEEE, New York, 1987, pp.
Gelsinger, "Design and Test of the 80386," IEEE Design and Test of Computers, June 1987, pp. 42-50. J. , 1982, pp. 269-286. 9 Chapter 2. An Introduction to Boundary-Scan This chapter provides an introduction to boundary-scan. It shows how the technique can provide an answer to the problems identified in Chapter 1. 1: Scan Testing at the Board Level At the chip level, the scan-design technique can be used to guarantee testability and to permit use of automatic test pattern generation (ATPG) tools .
1985.  J. Turino, "Enhancing Built-in Test on SMT Boards," Evaluation Engineering, June 1985.  C. Maunder, D. Roberts, and N. Sinnadurai, "Chip Carrier Based Systems and Their Testability," Hybrid Circuits, No. 5, Autumn 1984, pp. 29-36. N. , 1983, pp. 72-74.  M. , 1987, pp. 602-613.  R. Keeler, "Chip-on-Board Alters the Landscape of a PC Board," Electronic Packaging and Production, Vol. 25, July 7th 1985, pp. 62-67. L. Ginsberg, "Chip and Wire Technology: The Ultimate in Surface Mounting," Electronic Packaging and Production, Vol.
The Test access port and boundary-scan architecture by Jeffrey Liker, David Meier